The fabrication of integrated chips can be broadly separated into two main sections, front-end-of-the-line (FEOL) fabrication and back-end-of-the-line (BEOL) fabrication. FEOL fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) within a semiconductor substrate. BEOL fabrication includes the formation of one or more metal interconnect layers comprised within one or more insulating dielectric layers disposed above the semiconductor substrate. The metal interconnect layers of the BEOL electrically connect individual devices of the FEOL to external pins of an integrated chip.
For many years, aluminum was used as a metal for conductive materials for electrical connections, and silicon dioxide was used as an insulator. However, as devices are decreased in size, the materials for conductors and insulators have changed, to improve device performance. Copper is now often used as a conductive material for interconnects in some applications. Low dielectric constant (k) materials and extra-low k (ELK) materials that have dielectric constants less than that of silicon dioxide have begun to be implemented in some designs as insulating materials between interconnects.